1 application note 1612 isl6844 reference design: isl6844eval3z introduction this document focuses on intersil?s solution for the flyback converter. an inexpensive approach with discrete circuitry has been adopted instead of an integrated solution. low cost and optimal performance are the prime objectives. intersil?s superior industry-standard isl684x family of pwm controllers would best serve th e needs of this design. some key features of this fa mily of parts include: ? 40ns peak current sensing ?1a mosfet driver isl6844 was selected for its large uvlo hysteresis, uvlo start threshold, and the fact that the converter has been designed for a maximum operational duty cycle of 50%, thus protecting the ic by limiting the duty cycle in case of extreme fault conditions. specifications ? operating input voltage: 24v dc 10% ? output voltage: 15v ? output current: 100ma ? ripple: 50mv p-p ? switching frequency: 300khz ? topology: dcm flyback design procedure figure 1 shows a simplified circuit of the solution. it is assumed that loads are balanced for both positive and negative outputs. the turn ratio of the auxiliary winding is chosen to be the same as the secondary winding. figure 2 shows typical operational waveforms of a flyback converter in discontinuous conduction mode. determine the maximum duty cycle and transformer turn ratio isl6844 clamps the duty cycle to 50%. however, in this converter design, it is assumed that the operating maximum duty cycle, d max , will be 35% at the minimum input voltage of 21.6v. given the power level, the flyblack converter is designed to operate in discontinuous cond uction mode. the magnitizing inductance can be calculated using equation 1: where: = converter?s efficiency, assuming 75% p out = total output power f sw = switching frequency as a result, the peak magnitizing current = 1.06a the transformer?s turn ratio can be determined from: where: n = turns ratio between the primary and the secondary windings v f = forward drop across the diode, assuming 0.6v d 2 = duty cycle of diode conduction time d 2 t sw is the magnitizing current reset time. setting d 2 to 0.5, equation 2 yields the transformer?s turn ratio of 1. l m v in min , 2 d max 2 ? 2p out f sw ?? ----------------------------------------- ? = (eq. 1) 0.75 21.6 2 0.35 2 ? 2 3 300 3 10 ?? ------------------------------------- - 23.8 h = ? = n v out v f + () 1d 2 ? () ? v in min , d max ? ------------------------------------------------------- - = (eq. 2) d max d 2 + 1 < figure 1. simplified circuit +15v -15v d1 d2 c out1 c out2 vin cin cs rs ds vin out gnd fb vdd cs rsense isl6844 1n n n vreg c aux caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010, 2011. all rights reserved all other trademarks mentioned are the property of their respective owners. november 28, 2011 an1612.1
application note 1612 2 an1612.1 november 28, 2011 transformer core selection from figure 2, the rms current in the transformer primary side can be calculated from: the rms current in each transformer secondary side can also be computed from: the transformer used in this desi gn is pulse?s pa3374nl. it is a gapped ferrite toroid core, which has the following parameters: ?a e = 4.3mm 2 ?a l = 35nh/n 2 ?l e = 13.1mm ?v e = 56.5mm 3 this section provides general guideline to calculate the number of turn and wire size. for more details on designing transformer parameters, please contact a pulse representative. the number of turns on the primary side, np, can be determined from: therefore, the primary side has 26 turns. with the turn ratio of 1, the secondary side and the auxili ary primary side also have 26 turns. next the calculate the maximum flux density to make sure that it is below the saturation limit.where: for the operating power level, the wire sizes of the primary, secondary, and auxiliary windings are selected such that the current density in each winding is about 0.25335 cm 2 /a (50 circular mil/a) . to simplify transformer winding, awg#37 is used for all primary, secondary and auxiliary windings. primary mosfet selection the primary mosfet needs to be able to handle the voltage stress, given by: as a good design practice, some margin is provided to this peak stress voltage to accommodate tr ansient spikes and for a good reliable performance over time. providing a 30% design margin as a rule of thumb, the minimu m rating on the primary mosfet needs to be 54.6v. figure 2. typical operational current waveforms t sw dt sw d 2 t sw d 3 t sw i lm i pri i sec,1 i sec,2 i pk i pk mosfet on diodes (d1 and d2) off mosfet off diodes (d1 and d2) on mosfet off diodes (d1 and d2) off i rms pri , i pk d 3 -- - ? = (eq. 3) 1.06 0.35 3 ----------- 0.362a = ? = i rms sec , i pk 2 ------- d 2 3 ----- - ? = (eq. 4) 1.06 2 ----------- 0.5 3 ------- - 0.216a = ?? = n p luh [] 1000 a l ----------------------------------- - = (eq. 5) 23.8 1000 35 ------------------------------ - 26.07 = = b max l m i mmax , ? n p a e ? ------------------------------- - = (eq. 6) 23.8 6 ? 10 1.06 ? 26 4.3 2 ? 10 ? ------------------------------------------ - 4 10 0.226t = = a wpri , 0.25335 0.362 0.0917cm 2 = ? (eq. 7) v dsfet v = in max , nv out v f + () [] + (eq. 8) 26.4 1 15 0.6 + () [] 42v = + =
application note 1612 3 an1612.1 november 28, 2011 the rms current through the mosfet can be calculated from: selecting the conduction loss in th e mosfet to 1% of total output power, 0.03w. the required mosfet?s r ds(on) to achieve the required conduction loss is shown in equation 10. vishay?s si4436dy is selected in this design. output diode selection schottky diodes are recommended for the output diode due to their low forward voltage drop. the voltage stress across the output diode can calculated by: diodes inc?s b180 are employed in this design. output filter the output capacitance needs to meet the ripple and noise requirements, and also be able to handle the ripple current. assuming ceramic capacitors are used as the output filter, the voltage ripple from the capacitor?s esr is negligible. the minimum capacitance re quired to meet specifications can be approximately calculated from equation 12. 10f ceramic capacitors are selected for each output. design margin has been provided to account for noise spikes. snubber circuit when the mosfet switches off, it interrupts the current that flows through the transformer leakage inductance. an rcd snubber circuit is typically used in flyback converters to clamp voltage spikes on the mosfet. assuming that the transformer le akage inductance is 2% of the magnitizing inductance, the en ergy stored in the leakage inductance during mosfet?s on-time is: average power transferred to the snubber circuit is: to limit peak voltage spikes across the mosfet to 50v, the snubber voltage is set to: the average power transferred to the snubber circuit in equation 14 is dissipated by the snuuber resistor, so r s is determined by: so r s = 10k ? is selected. cs is se lected such that the r s c s time constant is substantially longer th an the switching period to keep low ripple voltage on the snubber circuit. a time constant of 10 times the switching period is used for calculation: c s = 3.33nf is used in the design. feedback network the feedback is being tapped off of the primary auxiliary winding. this is one of the advantages of selecting the flyback topology, since the auxiliary winding voltage follows the output. this scheme was fully exploited, since the load fluctuation is minimal, and that load regulation does not suffer much at these power levels. for tighter regulation requirements, an opto-coupled solution would need to be used, which leads to additional cost. referring to the schematic on page 8, the output voltage can be set by: r 23 = 1k ? and r 22 = 5.23k ? are selected. the control-to-output transfer function of the dcm flyback converter is [1]: where: r e = equivalent load resistor reflected to the auxiliary output. i rms fet , i pk d 3 -- - ? = (eq. 9) 1.06 0.35 3 ----------- 0.362a = ? = r ds on () p fet cond loss ? , i fet rms , 2 ------------------------------------------- = (eq. 10) 0.03 0.362 2 ----------------- - 0.229 = = v diode nv = in max , v out + (eq. 11) 1 26.4 15 41.4v = + = c out v pp 2 --------------- 1d 2 ? () t sw ? i out ------------------------------------- ? > (eq. 12) 0.42 f > 50 3 ? 10 2 --------------------- - 10.5 ? () 0.1 300 3 10 ? ----------------------------------- ? > w l 1 2 -- - l l i lm 2 ?? = (eq. 13) 1 2 -- - 0.02 23.8 6 ? 10 1.06 () 2 ?? ? 267.4nj = = p l w l f sw ? = (eq. 14) 267.4 9 ? 10 300 3 10 0.08w = ? = v s peakv mosfet v in min , ? = (eq. 15) 50 21.6 ? 28.4v = = r s v s 2 p l ------- = (eq. 16) 28.4 2 0.08 -------------- 10.08k = = c s 10 t sw r s ------------ ? (eq. 17) 10 = 3.33 6 ? 10 10 3 10 -------------------------- - 3.33nf = ? r 22 r 23 --------- - v out v f + v ref ----------------------------- 1 ? = (eq. 18) 15 0.6 + 2.514 -------------------- - 15.2 = ? = g vc k r e l m f sw ?? 2 ------------------------------------- 1sesrc ?? + 1s0.5r e c e ??? + () ------------------------------------------------------- ?? = (eq. 19)
application note 1612 4 an1612.1 november 28, 2011 c e = equivalent capacitor reflected to the auxiliary output. esr = equivalent series resist ance of the output capacitor. k = i spk(max) /v c(max) . the equivalent load reflected to the auxiliary output can be estimated from: the equivalent capacitor reflected to the auxiliary output can be estimated from: the value of i spk(max) can be determined by assuming that the auxiliary output delivers all of the output power. p out(max) = the maximum power allowed = 4w v c(max) has value of 1.1v, clamped by isl6844?s internal circuit. along with the result from equation 22, k has a value of 0.97. replaces k and the results from equation 21 and equation 22 into equation 19, yields note that with the low esr values of the output ceramic capacitor, the zero due to their esr is located at the frequency significantly higher than the swit ching frequency. as the result, the impact of capacitor?s esr is neglected for compensator design. from equation 20, it shows that when the total output power reduces, the equivalent load resi stor increases. this increases the dc-gain in equation 19, also the pole is moved to the lower frequency. from equation 23, the pole of the control-to-output transfer function for 3w output is located at 202hz. setting the closed-loop?s bandwidth of 10khz, the feedback compensation must have a mid-band gain of 3. 11 (10db). the mid-band gain is determined by therefore, r 24 is selected to be 16.2k ? . the first zero of compensation is set at 1/3 of the crossover frequency, 3.33khz. c 9 can be calculated from: 2.7nf is used for c 9 . the second zero of compensation is set at half of the switching frequency. c 10 can be calculated from: 68pf is used for c 10 . r e v aux 2 p out total () --------------------------------- - = (eq. 20) 15v () 2 3w ------------------ - 75 = = c e c aux n s1 n aux ------------- c ? out1 n s2 n aux ------------- c ? out2 ++ = (eq. 21) 1 f 15 15 ------ 10 f ? 15 15 ------ 10 f ? ++ 21 f = = i spk max () 2 p out max () v aux -------------------------------- ? d 2 ---------------------------------------- - = (eq. 22) 2 4w 15v ---------- - ? 0.5 ------------------ - 1.067a = = g vc 15.87 1 1 s 7.875 4 ? 10 ? + () ---------------------------------------------------- ? = (eq. 23 figure 3. gain of g vc 10 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 40 20 0 20 40 frequency (hz) gain (g vc ) 3w total output 1w total output a mid band ? r 24 r 22 --------- - = (eq. 24) c 9 1 2 3.33 3 10 16.2 3 10 ?? ? -------------------------------------------------------------------- = (eq. 25) 2.95nf = c 10 1 2 150 3 10 16.2 3 10 ?? ? ------------------------------------------------------------------ - = (eq. 26) 65.5pf =
application note 1612 5 an1612.1 november 28, 2011 printed circuit board the fixture of the pcb is a 2-laye r board with dimensions of 4 by 6 centimeters. all components are surface-mount packages and are placed in the top layer. reference [1] dixon, lloyd h., ?closing the feedback loop?, unitrode power supply design seminar, slup068, 1984. figure 4. evaluation board photo (top side) figure 5. evaluation board photo (bottom side) table 1. terminal terminals signals p1 vin (input voltage) p2 rtn (input ground return) p3 +15v (+15v output voltage) p4 +15v(-15v output voltage) p5,p6 gnd (output ground)
application note 1612 6 an1612.1 november 28, 2011 typical performance curves figure 6. start up at no load figure 7. start up at full load figure 8. output ripples at no load figure 9. output ripples at full load figure 10. efficiency figure 11. output voltage regulations 40 45 50 55 60 65 70 75 80 85 efficiency (%) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 total output power (w) 17.5 17.0 16.5 16.0 15.5 15.0 14.5 output voltages (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 total output power (w) ioutp = ioutn voutp voutn
application note 1612 7 an1612.1 november 28, 2011 figure 12. over current response typical performance curves (continued)
application note 1612 8 an1612.1 november 28, 2011 schematic power input 24v dnp vref rs 10k 1 2 p2 vin- 1 c6 150pf 1 2 r1 0.82ohm 1 2 c13 1nf/2kv 1 2 cs 3.3nf 1 2 t1 1 4 3 2 5 6 7 8 p3 +15v 1 d5 b180 2 1 r22 10k 1 2 u1 isl6844 rtct 4 cs 3 gnd 5 out 6 comp 1 fb 2 vdd 7 vref 8 c3 10uf 1 2 c4 1uf 1 2 d4 b180 2 1 c18 0.1uf 1 2 c12 220pf 1 2 r11 5.1 1 2 q2 si4436dy r6 100 1 2 c24 10uf 1 2 r14 6.49k 1 2 r24 16.2k 1 2 p4 -15v 1 c11 10uf 1 2 p1 vin+ 1 d2 bat46w 2 1 r25 4.02k 1 2 p5 rtn 1 c10 68pf 1 2 d3 bat46w 2 1 r4 10k 1 2 r15 10 1 2 c23 10uf 1 2 d1 bat54 2 1 c8 1uf 1 2 r3 12.1k 1 2 d7 bzt52c18 r10 5.1 1 2 c9 2.7nf 1 2 p6 rtn 1 c17 0.1uf 1 2 c16 0.1uf 1 2 r5 1k 1 2 r23 2k 1 2 r26 4.02k 1 2 c14 0.1uf 1 2 c15 2.2uf 1 2
application note 1612 9 an1612.1 november 28, 2011 bill of materials ref des qty part number description package vendor u1 1 isl6844iuz ic, pwm controller msop-8 intersil q2 1 si4436dy mosfet, n-channel, 60v sop-8 vishay d1 1 bat54ws schottky diode, 30v sod323f diodes inc. d2, d3 2 bat46w schottky diode, 100v sod123 diodes inc. d4, d5 2 b180 schottky diode, 80v, 1a sma diodes inc. d7 dnp bzt52c18 zener diode 18v sma diodes inc. t1 1 pa3374nl transformer, custom pulse c3 1 c5750x7r1h106k capacitor, ceramic, x7r, 10f, 20%, 50v sm_2210 generic c4 1 capacitor, ceramic, x7r, 1.0f, 20%, 50v sm_0805 generic c6 1 capacitor, ceramic, x5r, 150pf, 20%, 50v sm_0603 generic c8 1 capacitor, ceramic, x5r, 1.0f, 20%, 25v sm_0805 generic c9 1 capacitor, ceramic, x5r, 2.7nf, 20%, 50v sm_0603 generic c10 1 capacitor, ceramic, x5r, 68pf, 20%, 50v sm_0603 generic c11 1 capacitor, ceramic, x5r, 10f, 20%, 25v sm_1206 generic c12 1 capacitor, ceramic, x7r, 220pf, 20%, 50v sm_0603 generic c13 1 C4520X7R3D102K capacitor, ceramic, x7r, 1000pf, 10%, 2kv sm_1808 tdk c14, c16, c17, c18 4 capacitor, ceramic, x7r, 100nf, 10%, 50v sm_0603 generic cs 1 capacitor, ceramic, x7r, 3.3nf, 20%, 50v sm_0805 generic c15 1 capacitor, ceramic, x7r, 2.2f, 20%, 10v sm_0603 generic c23, c24 2 capacitor, ceramic, x5r, 10f, 10%, 25v sm_1812 generic r1 1 resistor, 0.82 , 1%, 1/4w sm_1206 generic r3 1 resistor, 12.1k , 1%, 1/16w sm_0603 generic r4, r22 2 resistor, 10k , 5%, 1/16w sm_0603 generic r5 1 resistor, 1k , 1%, 1/16w sm_0603 generic r6 1 resistor, 100 , 1%, 1/16w sm_0603 generic r10, r11 2 resistor, 5.1 , 1%, 1/16w sm_0603 generic r14 1 resistor, 6.49k , 1%, 1/16w sm_0603 generic r15 1 resistor, 10 , 1%, 1/16w sm_0603 generic rs 1 resistor, 10k , 5%, 1/4w sm_1206 generic r23 1 resistor, 2k , 1%, 1/16w sm_0603 generic r24 1 resistor, 16.2k , 5%, 1/16w sm_0603 generic r25, r26 2 resistor, 4.02k , 5%, 1/16w sm_0603 generic
application note 1612 10 intersil corporation reserves the right to make changes in circuit design, software and/or specifications at any time without n otice. accordingly, the reader is cautioned to verify that the application note or technical brief is current before proceeding. for information regarding intersil corporation and its products, see www.intersil.com an1612.1 november 28, 2011 isl6844eval3z printed circuit board layers figure 1. isl6844eval3z - top layer (silkscreen) figure 2. isl6844eval3z - top layer (component side) figure 3. isl6844eval3z - bottom layer (solder side) figure 4. isl6844eval3z - bottom layer (silkscreen)
|
